1. Field of the Invention
The present invention relates to a method for forming contact to allow circuit elements formed on a highly-integrated semiconductor substrate to be electrically connected to multi-layered metal lines, and more particularly to a method for forming self-aligned contact capable of improving packing density of a semiconductor device by minimizing the contact area.
2. Description of the Prior Art
Generally, a semiconductor device having integrated circuits such as dynamic random access memories (DRAMs) includes contact electrically connected to a drain diffusion region of penetrating an insulating layer between adjacent gates of a field-effect transistor. The contact functions to extract an electrode at the drain diffusion region by connecting the drain diffusion region to the metal lines.
The self-aligned contact minimizes not only a spacing between adjacent gates but also a contact hole area formed into the insulating layer between the adjacent gates to increase the packing density of the semiconductor device. However, the self-aligned contact has a problem of involving shorts between the metal lines and gate electrodes having high critical steps caused by critical-area deviation of a mask, tolerance of misalignment, distortion of lens, thickness of the insulating layer, etc. The problem of the conventional self-aligned contact will be described with reference to FIGS. 1 to 3.
FIG. 1 shows a layout of a semiconductor device having four bit line regions B arranged between active regions A of a predetermined width, and contact regions C disposed to overlap the bit line regions at the upper and lower ends of them. In order to improve the packing density of the semiconductor device, the bit line regions A are arranged to be close to each other as much as possible. The self-aligned contact occupying a smaller area is formed in the contact region C to minimize the spacing between the bit line regions B (i.e., the width of the active region A).
FIGS. 2A to 2D are sectional views showing the semiconductor device, taken along line a--a' of FIG. 1, which illustrate steps of forming the conventional self-aligned contact.
Referring to FIG. 2A, the semiconductor device includes a substrate 10 having impurity diffusion regions 11 which are provided in the active region A shown in FIG. 1 and separated from each other by a field oxide layer (not shown) formed on an unshown field region. A first insulating layer 12, a first conductive layer 13 and a second insulating layer 14 are sequentially formed on the surface of the substrate 10.
As shown in FIG. 2B, the first insulating layer 12, first conductive layer 13 and second insulating layer 14 are sectioned to be a first insulating pattern 12A, a first conductive pattern 13A and a second insulating pattern 14A, which are formed by etching portions of the first insulating layer 12, first conductive layer 13 and second insulating layer 14 formed on the impurity diffusion region 11, using a bitline mask. The first conductive pattern 13A serves as the bit line. A third insulating layer 15 is formed over the surface of the substrate 10 having the first insulating pattern 12A, first conductive pattern 13A and second insulating pattern 14A thereon, and a photoresist pattern 16 for contact mask is formed on the third insulating layer 15.
FIG. 2C illustrates a contact hole 20 formed by etching the third insulating layer 15 exposed by the photoresist pattern 16 to expose both a predetermind upper portion of the second insulating pattern 14A and the surface of the impurity diffusion region 11, and a spacer 15A formed of the third insulating material. The photoresist pattern 16 shown in FIG. 2B is removed after the etching process. The spacer 15A is placed along the sidewalls of the first insulating pattern 12A, first conductive pattern 13A and second insulating pattern 14A. A second conductive layer 17 on the contact hole 20 is formed by depositing a metal, and a photoresist pattern 18 for storage electrode mask is formed on the second conductive layer 17.
Referring to FIG. 2D, a second conductive pattern 17A is formed by selectively etching the third conductive layer 17 exposed by the photoresist pattern 18 shown in FIG. 2C. The photoresist pattern 18 is removed after the etching process of the second conductive layer 17 is carried out. Residue 17B of the third conductive layer 17 remaining on the steps of the third insulating layer 15 without being eliminated during the etching process of the second conductive layer 17 is originated due to the relatively high step at the surface of the third insulating layer 15. The residue of the third conductive layer 17 induces shorts in other metal lines to be formed later in a step followed by the contact formation step to therefore degrade the semiconductor device.
For the purpose of preventing the high steps of the insulating layer and eliminating the conductive material remaining at the surface of the insulating layer according to the conventional method for forming the self-aligned contact as shown in FIGS. 2A to 2D, another method for forming the self-aligned contact has been suggested which will be described with reference to FIGS. 3A to 3C.
Referring to FIG. 3A, a semiconductor device includes a substrate 10 having an impurity diffusion region 11 on a predetermined portion thereof, a first insulating layer 12 on the surface of the substrate 10, and a first conductive pattern 13A for gate electrode patterned on the first insulating layer 12. A second insulting layer 14 which will be used as an insulating interlayer is deposited on the upper portion of the first conductive pattern 13A and first insulating layer 12. Also, a photoresist pattern 16 for contact mask is formed on the second insulating layer 14.
A contact hole 20 shown in FIG. 3B is formed by etching the second insulating layer 14 exposed by the photoresist pattern 16 and the first insulating layer 12 positioned under the exposed second insulating layer 14. The photoresist pattern 16 is removed after forming the contact hole 20. The lower surface of the contact hole 20 is in contact with the surface of the impurity diffusion region 11. Then, a third insulating layer 15 is formed both in the contact hole 20 and over the surface of the second insulating layer 14.
FIG. 3C illustrates a step of etching-back the third insulating layer 15 formed by the step shown in FIG. 3B to expose the impurity diffusion region 11, thereby forming a spacer 15A of the third insulating material along the sidewall of a gate electrode pattern consisting of the first insulating layer 12, first conductive pattern 13A and second insulating layer 14, and along the sidewall of the contact hole 20 consisting of a first insulating layer pattern 12A and a second insulating pattern 14A. A second conductive pattern 17A electrically connected to the impurity diffusion region 11 on the substrate 10 is formed by a mask-patterning process of depositing a second conductive layer 17 in the contact hole 20 and on the upper portion of the second insulating layer 14 having the spacer 15A and selectively removing the second conductive layer 17.
However, the method for forming the conventional self-aligned contact as shown in FIGS. 3A to 3C has a problem of inducing shorts at the first conductive layer 13A and second conductive pattern 17A when the portions of the third insulating layer 15 stacked on the surface of the second insulating layer 14 and stacked on the impurity diffusion region 11 are thicker than the portion of the third insulating layer 15 stacked on the surface of the exposed first conductive pattern 13A. In addition to the short, since the third conductive layer 15 stacked on the upper portion of the first conductive pattern 13A must be thickened to prevent the short at the first and second conductive patterns 13A and 17A, the spacing of gate pattern used as the bit lines and contact area cannot be reduced to below a predetermined size.